This invention pertains to a ratio circuit, and in particular a MOS transistor ratio circuit for a latch and other digital circuits utilizing a ratio circuit.
As illustrated by curve LA in FIG. 14, MOSFETS (metal-oxide semiconductor field-effect transistors) and other MOS devices exhibit the so-called short-channel effect, which is a phenomenon in which the threshold voltage Vth decreases with the length of the channel or gate. When the short-channel effect is pronounced, punch-through takes place, so that the current between the source and drain cannot be controlled by the gate voltage. Consequently, in order to ensure normal functioning of MOS transistors, it is necessary to prevent the short-channel effect and punch-through.
Various technologies have been developed or proposed to suppress the short-channel effect. For example, a recent processing technology that uses a gate length of 0.21 xcexcm as the design rule adopts the LDD (lightly doped drain) structure shown in FIG. 15. In this structure, below the low-concentration diffusion region (Nxe2x88x92) on the channel side end portion of the drain and source regions, the opposite conductivity type low-concentration diffusion region (Pxe2x88x92) is formed by means of impurity ion implantation at a prescribed angle of incidence [xcex8]. In this way, expansion from the drain and source regions to the depletion region can be effectively suppressed. Curve LB in FIG. 14 shows a profile with maximum threshold voltage Vth near the minimum gate length (0.21 xcexcm) to satisfy the design rule. That is, the so-called inverse short-channel effect is realized.
The example shown in FIG. 15 pertains to an N-channel MOS transistor. However, the same technology applies to the P-channel MOS transistor. In FIG. 14, characteristic curves LA and LB refer to the results of simulation and experiment for the N-channel MOS transistor, respectively. The same characteristic curves can be obtained with the P-channel MOS transistor. However, in this case, the rate of increase of Vth in the inverse short-channel effect is a little smaller (lower).
FIG. 16 is a diagram illustrating an example of the conventional CMOS ratio circuit having the aforementioned MOS transistors with the inverse short-channel effect. In this ratio circuit, N-channel MOS transistor 202 of CMOS (complementary metal oxide semiconductor) circuit 200 forms the driving element, while P-channel MOS transistor 206 of CMOS circuit 204 on the other side forms the load element. The drain terminals of said N-channel MOS transistor 202 on the driving side and said P-channel MOS transistor 206 on the load side are electrically connected via transfer gate 208. Usually, node 210 between said two transistors 202 and 206 is connected as the output terminal of this ratio circuit to the other circuit (not shown in the FIG.).
When both MOS transistors 202 on the driving side and MOS transistor 206 on the load side are on, transfer gate 208 is on. In this state, current i has the following circuit path: power source terminal of power source voltage Vddxe2x86x92P-channel MOS transistor 206 on the load side xe2x86x92transfer gate 208xe2x86x92N-channel MOS transistor 202 on the driving sidexe2x86x92ground terminal.
In this ratio circuit, the conductance of MOS transistor 202 on the drive side is made higher than that of MOS transistor 206 on the load side. In this way, when both transistors are on, they are electrically mismatched, so that the output voltage at node 210 shifts toward the reference voltage (ground potential) on the side of MOS transistor 200.
FIG. 17 illustrates the layout of two MOS transistors 202 and 206. For MOS transistor 202 on the driving side, in order to raise the operating speed to the maximum, the gate length Li is set as the minimum gate length dimension (e.g., 0.21 xcexcm) of the design rule, and, in order to increase the current capacity, the channel width Wi is selected to have a relatively large dimension (e.g., 0.91 xcexcm). On the other hand, for MOS transistor 206 on the load side, in order to realize a load function with a high ON-resistance (a low conductance), the gate length Lj is selected to a dimension (e.g., 0.35 xcexcm) significantly larger than the minimum gate length dimension. Also, channel width Wj is selected to have a dimension (e.g., 0.56 xcexcm) smaller than that on the driving side.
In this way, since MOS transistor 202 on the driving side has gate length Li of the minimum gate length dimension of the design rule, operation is performed at a high threshold voltage Vth due to the inverse short-channel effect. On the other hand, for MOS transistor 206 on the load side, since the gate length Lj is significantly larger than the minimum gate length dimension of the design rule, operation is performed at a relatively low threshold voltage Vth without the influence of the inverse short-channel effect (also without the influence of the short-channel effect).
In recent years, with the progress made in realizing higher levels of integration and higher density of semiconductor ICs, in consideration of the reduction of power consumption, there has been a demand for the operation of various types of electronic equipment at lower power source voltage. In particular, there has been an increasing demand for guaranteeing the operation of portable battery-powered electronic equipment even when the power source voltage drops below 1 V.
The present inventors have extensively studied the performance and operation of the ratio circuit and found that in the conventional design method, due to influence of the inverse short-channel effect, there is an operating limit near 0.95 V. However, assuming a nominal voltage of 1.0 V, since there should be certain tolerance (margin), operation should be guaranteed down to 0.9 V, that is, 10% below the nominal voltage. Consequently, an operating limit near 0.95 V is insufficient.
Also, since the threshold voltage Vth of the MOS transistor rises as the temperature decreases, the influence of the inverse short-channel effect becomes stronger at low temperatures, and the operating limit value may become even higher.
FIGS. 18, 19 and 20 respectively illustrate ID-VGS characteristic curves for three models of xe2x80x9cWEAK,xe2x80x9d xe2x80x9cNOMINAL,xe2x80x9d and xe2x80x9cSTRONGxe2x80x9d obtained in the SPICE simulation in the case of the design of MOS transistors with channel width W selected as 0.21 (constant) and gate length L selected as 0.21 xcexcm and 0.35 xcexcm (two types) at ambient temperature of xe2x88x9240xc2x0 C. For example, as can be seen from FIG. 18, threshold voltage Vth that corresponds to a given characteristic curve can be assumed to be the voltage value at the intersection of the straight line drawn tangent to the linear portion of the characteristic curve and the voltage axis.
Variations in the fabrication process lead to variations in device characteristics. In this example, the WEAK model refers to the fact that threshold voltage Vth is relatively high and the current driving ability is relatively low (weak). On the other hand, the STRONG model refers to the case when threshold voltage Vth is relatively low and the current driving ability is relatively high (strong). The NOMINAL model refers to the intermediate case between the two aforementioned models. Also, for general-purpose conventional products, the Ta specification is 0 to 70xc2x0 C. On the other hand, for communication ICs, it is in the range of xe2x88x9240xc2x0 C. to 85xc2x0 C. Consequently, xe2x88x9240xc2x0 C. can be regarded as the worst-case temperature at which operation can be assured.
As can be seen from FIGS. 18, 19 and 20, when the power source voltage (nearly equal to gate-source voltage VGS) of a MOS transistor with a gate length of 0.21 xcexcm falls close to 0.9 V, the transistor will be operating in the sub-threshold region since the threshold voltage Vth will have been raised by the inverse short-channel effect. In this sub-threshold region, since the S-factor is about 80 mV/dec, even a decrease in the voltage of 0.08 V leads to a decrease in the leakage current by one order of magnitude. Consequently, the operation is governed by the sub-threshold current instead of the original driving current.
On the other hand, even at a low power source voltage of about 0.9 V, a MOS transistor with a gate length of 0.35 xcexcm will be able to maintain operation essentially in the linear region since there is no influence of the inverse short-channel effect (there is also no influence of the short-channel effect), and threshold voltage Vth is relatively low (about 0.76 V).
Consequently, in the conventional ratio circuit, MOS transistor 202 on the drive side operating in the sub-threshold region and MOS transistor 206 on the load side operating in the linear region are electrically mismatched and the desired operation, that is, the operation with the potential of node 210 between them shifting toward the reference potential on the driving side cannot be guaranteed. That is, a design in which the operation is determined on the basis of the conductance or the ON-resistance cannot be established.
In order to solve the aforementioned problem, it has been proposed that the current-driving ability of MOS transistor 202 on the drive side at a low power source voltage should be raised, and its channel width W should be further increased. However, when a decrease in the current-driving ability of the S-factor is compensated for, channel width W becomes so large that it is unrealistic with respect to the layout.
Also, at present, the specifications are for adopting a low power source voltage of 1 V or less and a conventional power source voltage of, e.g., 1.8 V, at the same time. Consequently, not only the operation should be guaranteed under the low power source voltage, but also the performance of operation under the conventional power source voltage should not degrade. Also, for MOS transistor 202 on the driving side, if channel width W is increased significantly, the gate capacitance rises, leading to a deterioration in the performance (power consumption, speed, etc.) in the mode of operation under the conventional power source voltage.
Also, in consideration of the design database and the cell library, it is inconvenient to prepare and use two types, one for operation at conventional voltage and the other for operation at low voltage.
The purpose of this invention is to solve the aforementioned problems of the conventional technology by providing a type of ratio circuit and a type of latch circuit with improvement in guaranteeing the operation at low power source voltage.
Another purpose of this invention is to provide a ratio circuit and a latch circuit which make active use of the inverse short-channel effect to guarantee stable operation at low power source voltage.
Yet another purpose of this invention is to provide a ratio circuit and a latch circuit which can guarantee stable operation over a wide range of power source voltages, including 1 V or less.
Yet another purpose of this invention is to provide a ratio circuit and a latch circuit which can guarantee stable operation at low power source voltage without substantially increasing the surface area of the circuit.
Yet another purpose of this invention is to provide a MOS transistor which can guarantee a high ON-resistance and operates under the influence of the inverse short-channel effect without substantially increasing the surface area of the circuit.
In order to realize the aforementioned purpose, the ratio circuit of this invention has a configuration in which a first MOS transistor having a single channel with inverse short-channel effect and a second MOS transistor having plural channels each having inverse short-channel effect and connected in tandem are electrically connected to each other.
In the ratio circuit of this invention, if both the first and second MOS transistors with inverse short-channel effect are conducting, they will be electrically mismatched. Since the two MOS transistors have similar threshold voltages, at a low power source voltage near the threshold voltage, both MOS transistors will operate in the sub-threshold region. In this case, due to a difference in the number of channels connected in tandem between the two MOS transistors, the second MOS transistor operates at a higher ON-resistance. Consequently, the current driving ability of the first MOS transistor predominates, and the potential of the node between the two MOS transistors shifts toward the potential of the first MOS transistor.
In the ratio circuit of this invention, the first and second MOS transistors may either P-channel conductivity type or N-channel conductivity type. Also, for the two MOS transistors, the terminals connected to each other and the terminals on the opposite side may be connected to any power source voltage terminal or other element or circuit, and it is possible to apply any signal or voltage to each gate terminal.
A typical form of the ratio circuit of this invention has a first MOS transistor of the first conductivity type which has a single channel with inverse short-channel effect and which has its source terminal connected to a first reference voltage terminal that feeds the first potential, and a second MOS transistor of the second conductivity type which has plural channels each having the inverse short-channel effect and connected in tandem, and which has its source terminal connected to a second reference voltage terminal that feeds a second potential different from said first potential and has its drain terminal electrically connected to the drain terminal of said first MOS transistor.
In the latch circuit of this invention, the first MOS transistor forms the driving element, while the second MOS transistor forms the load element. When the latch circuit of this invention is CMOS, it also has a third MOS transistor of the second conductivity type which has its source terminal connected to said second reference voltage terminal and has its drain terminal connected to the drain terminal of said first MOS transistor, with the gate terminal supplied with the same gate voltage as for the gate terminal of said first MOS transistor, and a fourth MOS transistor of the first conductivity type which has its source terminal connected to said first reference voltage terminal and has its drain terminal connected to the drain terminal of said second MOS transistor, with the gate terminal supplied with the same gate voltage as for the gate terminal of said second MOS transistor.
In this CMOS form, said third MOS transistor has a single channel with inverse short-channel effect, and said fourth MOS transistor has plural channels each having inverse short-channel effect and connected in tandem. For said third and fourth MOS transistors, the former acts as a driving element, while the latter acts as a load element.
For the MOS transistor of this invention, the intermediate regions multiply divide the channel between the source region and drain region, and the divided channels are connected in tandem, with each divided channel displaying the inverse short-channel effect.
In order to realize the inverse short-channel effect for each divided channel, the prescribed semiconductor region is formed on a principal surface of the semiconductor substrate or semiconductor layer between the source region and the intermediate region and between the drain region and the intermediate region.
The semiconductor region acts to relax the electric field near the ends of the source region, intermediate region and drain region facing the dividing channels, and to inhibit the extension of the depletion layer. For example, the semiconductor region may have a first region of the second conductivity type, which has a different impurity concentration than said source region, said drain region and said intermediate region and which is placed in contact with said insulating film, and a second region, which has a different impurity concentration than said semiconductor substrate or semiconductor layer and which is formed beneath it in contact with said first region.